1. Field of the invention
The present invention relates to a thin film transistor(TFT) with an inverted stagger type structure, and further, to a method of manufacturing such a transistor. The transistor is utilized as a switching device of an active matrix LCD(Liquid Crystal Display) for example and has a polycrystalline semiconductor layer as an active layer.
2. Description of the Related Art
A conventional thin film transistor has an amorphous silicon layer as the active layer. Carrier mobility of polycrystalline silicon is higher than that of amorphous silicon. Use of a polycrystalline silicon layer as the active layer has been recently examined to improve performance of the transistor.
A glass substrate is exposed to an atmosphere of approximately 300.degree. C. to form the amorphous silicon layer on it. The glass substrate is also exposed to an atmosphere of approximately 600.degree. C. to form the polycrystalline silicon layer on it. For example, the polycrystalline silicon layer may be directly accumulated on the glass substrate by an LPCVD (Low Pressure Chemical Vapor Deposition) method at 600.degree. C., or formed by solid-phase crystallizing amorphous silicon at 600.degree. C. for twenty hours. A hard glass substrate which contains no alkaline metal has been utilized as the glass substrate because of its low price. When the hard glass substrate which contains no alkaline metal is exposed to an atmosphere of more than 550.degree. C., it begins to shrink. Therefore, when the polycrystalline silicon layer is formed on the hard glass substrate which contains no alkaline metal, the hard glass substrate shrinks. In this case, the size of a pattern existing on the hard glass substrate after the polycrystalline silicon layer is formed does not correspond to the size of a pattern before the polycrystalline silicon layer is formed because of the shrinkage. Consequently, it is impossible to execute a mask alignment process after the polycrystalline silicon layer is formed. Therefore, it has been difficult to utilize the hard glass substrate.
Several alternatives have been proposed for reducing the problems caused by shrinkage of the hard glass. One of the alternatives is to make the size of the substrate small. Another alternative is to use quartz as the material of the substrate. Yet another alternative is to raise the temperature that the substrate can withstand before shrinking occurs. However, when the size of the substrate is small, it is impossible to enlarge a display area of the active matrix LCD. When material of the substrate is quartz, the price of the substrate becomes high. There has been no substrate suggested to date which can resist shrinking at 600.degree. C.
With regard to the manufacturing process, a thin film transistor structure shown in FIG. 15 has been examined. The structure is of a so-called staggered type in which a gate is disposed over the active layer. A source and a drain are formed at comparatively low temperature in the manufacturing process. Two concrete manufacturing process will be explained below.
A first manufacturing process will be explained with reference to FIGS. 9 and 11-15. FIG. 9 shows a transparent substrate 10. A polycrystalline silicon layer 13 is formed on the transparent substrate 10. A semiconductor layer 15 is formed on the polycrystalline silicon layer 13. The semiconductor layer 15 has a high-concentration of impurities. A metal electrode layer 16 is formed on the semiconductor layer 15. The semiconductor layers 15a and 15b and the metal electrode layers 16a and 16b are formed by selectively photoetching as shown in FIG. 11. The semiconductor layer 15a and the metal electrode layer 16a correspond to a source region. The semiconductor layer 15b and the metal electrode layer 16b consist of a drain region. The polycrystalline silicon layer 13 is then selectively photoetched as shown in FIG. 12. The photoetched layer 13 corresponds to an active region, or a channel region. A gate insulating layer 12 is formed on the transparent substrate 10, the polycrystalline silicon layer 13, and the metal electrode layers 16a and 16b as shown in FIG. 13. A gate electrode 11 is selectively formed on the gate insulating layer 12. A passivation film 14 is then formed on the gate insulating layer 12 and the gate electrode 11 as shown in FIG. 14. Thereafter, contact holes are opened in the gate insulating layer 12 and the passivation film 14. Electrodes 19a and 19b are formed in the contact holes. FIG. 15 shows the normal staggered type thin film transistor manufactured by the above-mentioned process.
A second manufacturing process will be explained with reference to FIGS. 10-15. FIG. 10 shows the polycrystalline silicon layer 13 formed on the transparent substrate 10. A sacrifical layer 17 for a so-called lift-off process is selectively formed on the polycrystalline silicon layer 13. The sacrifical layer 17 is formed on only the region on which the source and drain regions will be not formed. The semiconductor layer 15 and the metal electrode layer 16 are then formed on the polycrystalline silicon layer 13 and the sacrifice layer 17 in this order. The intermediate structure shown in FIG. 11 is formed by lifting off the sacrifical layer 17. The transistor shown in FIG. 15 is formed by carrying out the processes which have been explained above with reference to FIGS. 12-14.
According to the above-mentioned first and second manufacturing process, the polycrystalline silicon layer 13 is formed before the source and drain regions are formed. Therefore, even if the transparent substrate 10 shrinks when the polycrystalline silicon layer 13 is formed, it is possible to execute the mask alignment process for forming the source and drain regions. It is therefore possible to use the hard glass substrate which contains no alkaline metal as the transparent substrate 10.
However, according to the first manufacturing process, when the semiconductor layer 15 is etched, the polycrystalline silicon layer 13 is also etched a little and is damaged. Therefore, characteristics of the manufactured thin film transistor become unstable.
On the other hand, according to the second manufacturing process, because the source and drain regions are formed by the lift-off process, it is difficult to control shapes of edges of the source and drain regions. Therefore, the gate insulating layer 12 formed on the source and drain regions cracks, and gate withstanding voltage becomes low.